The present invention relates to a semiconductor device having an electrically programmable non-volatile memory, and a data processor. The present invention also relates to a technology for solving a delay in read access due to precharge and discharge operations of each bit line, which are necessary for the operation of reading memory information held in each non-volatile memory cells of the non-volatile memory, e.g., a technology effective for application to a microcomputer equipped with a flash memory in an on-chip form.
A flash memory, which is one electrically writable or programmable memory, has non-volatile memory cells each comprising one memory cell transistor having a floating gate, a control gate, a source and a drain, for example. In the memory cell transistor, a threshold voltage thereof rises when electrons are injected into the floating gate, whereas when the electrons are extracted from the floating gate, its threshold voltage drops. The memory cell transistor serves so as to store information corresponding to the magnitude or high and low levels of a threshold voltage relative to a word line voltage (voltage applied to control gate) for reading data. Although not restricted in particular, the state in which the threshold voltage of the memory cell transistor is low, is called an xe2x80x9cerase statexe2x80x9d, and the state in which the threshold voltage thereof is high, is called a xe2x80x9cwrite statexe2x80x9d.
In order to read information held in each of the non-volatile memory cells, the drain side (bit line side) of the selected non-volatile memory cell is clamped to a precharge voltage and a gate voltage is applied. If the electrons have been stored in the non-volatile memory cell, the threshold voltage is high and no current flows even if the gate voltage is applied. If no electrons are stored in the memory cell, the threshold voltage is low and the current flows when the gate voltage is applied.
A sense amplifier detects such a state. Now consider where the sense amplifier is of a current sense type sense amplifier, for example. When the sense amplifier causes a current equivalent to half of a memory cell current (corresponding to a current flowing in each memory cell held on) to flow, a bit line voltage of a memory cell high in threshold voltage becomes higher than a precharge voltage. A bit line voltage of a memory cell low in threshold voltage becomes lower than the precharge voltage. A logic value of memory information held in the corresponding memory cell is judged according to the difference between the above voltages. Even when the sense amplifier belongs to a non-current sense type configuration, e.g., it is of a differential sense amplifier of such a type that a bit line voltage is compared with a reference level, there is a need to precharge the corresponding bit line to the reference level or a level close to it in advance before the start of a read operation. In order to read the information of the memory cell in this way, there is a need to clamp the corresponding bit line to the precharge voltage.
On the other hand, let""s look at the memory cell. If the voltage is always applied to the source side (source line side) or drain side (bit line side), such an electric field that electrons are stored in or extracted or drawn from the floating gate, is formed, thus causing a possibility that memory information will be damaged (disturbed). It is not desirable that the voltage like the precharge voltage is always applied to the drain of each memory cell via its corresponding bit line in order to prevent the fear of such disturb before happens.
Therefore, there is a need to set the source and drain sides of the memory cell as a ground potential when no reading is done. The bit line must be discharged because the precharge voltage is clamped before the reading and the voltages on the source and drain sides are set to the ground potential rapidly after the reading. In order to reduce capacitance parasitic on each bit line connected with the drain of the memory cell in particular, a main/sub bit line structure is frequently adopted. In the main/sub bit line structure, only a sub bit line connected with a memory cell intended for a read operation is connected to its corresponding main bit line.
However, in order to read memory information of a non-volatile memory cell, there is a need to carry out pre-reading bit line precharge and post-reading bit line discharge. Even if the operating time (corresponding to the time required to make a decision as to whether a main bit line voltage is larger or smaller than a precharge voltage) necessary to read memory information could be shortened owing to the configuration or the like of the sense amplifier, the shortening of the time intervals for the precharge and discharge have been not yet implemented. With the trend toward an increase in parasitic capacitive component due to an increase in storage capacity, the precharge and discharge time intervals become long in reverse.
An object of the present invention is to shorten the time necessary to charge and discharge a bit line to which a non-volatile memory cell is connected.
Another object of the present invention is to speed up the reading of memory information from a non-volatile memory cell without performing an improvement in the performance of a sense amplifier, etc.
A further object of the present invention is to provide a data processor capable of contributing to the speeding up of data processing in terms of the reading of memory information from a non-volatile memory cell at high speed.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
A semiconductor device according to the present invention has an electrically programmable non-volatile memory. The non-volatile memory includes a plurality of non-volatile memory cells (MC), word lines (X00 through Xkn) respectively connected to select terminals of the non-volatile memory cells, sub bit lines (LB00 through LBkm) respectively connected to data terminals of the non-volatile memory cells, main bit lines (MB0 through MBm), sub bit line selection switch elements (Q00 through Qkm) which selectively connect the sub bit lines to the main bit lines, a sense amplifier (30) connected to the main bit lines via column switch elements (QY0 through QYm), and voltage supply elements (QPC0 through QPCm) each of which supplies a predetermined clamp voltage to each of the main bit lines. The clamp voltage is a predetermined level between a high-level side attainment level outputted from the sense amplifier and a low-level side attainment level outputted therefrom. Each of the voltage supply elements supplies the clamp voltage to the corresponding main bit line during at least a period prior to and subsequent to a read operation for each of the non-volatile memory cells.
According to the above means, the clamp voltage is supplied from each of the voltage supply elements to its corresponding main bit line during at least the period prior to and subsequent to the read operation for each non-volatile memory cell. Accordingly, there is no need to precharge the main bit line from the ground level upon the operation of reading the memory information, and the read operating time can hence be shortened. Since the non-volatile memory becomes fast in operating speed, the operating speed or throughput of the whole data processing system using it can be enhanced.
The clamp voltage is a level desirable in terms of a sense operation of the sense amplifier. The clamp voltage is, for example, a criterion level of the sense amplifier or a level higher than the criterion level. A discharge for each sub bit line is not necessary either for a non-volatile memory cell having a device structure free of the occurrence of disturb at that level.
In order to stabilize the operation of sensing by the sense amplifier even with respect to the small amount of a signal read from the memory cell and thereby speed up the determination of the sense operation, the voltage supply element may preferably stop the operation of supply of the clamp voltage during the period of the read operation for the non-volatile memory cell.
In order to previously prevent the fear of disturb, discharge elements (QD00 through QDkm) for respectively discharging the sub bit lines when the sub bit line selection switch elements are respectively held off, may preferably be adopted. That is, the precharge for each main bit line, i.e., the supply of the clamp voltage and the discharge for each sub bit line are performed in parallel. Supplying the clamp voltage to the main bit line so as to avoid mutual interference of such parallel operations may be performed when the sub bit line selection switch element is held off.
In order to shorten a precharge time prior to the reading of memory information with a main/sub bit line structure as a premise from the above, the main bit line is clamped to a precharge voltage in advance, and the drain (sub bit line) of each memory cell is maintained at a ground potential. There is therefore no problem of memory disturb. Since the time required to charge each main bit line becomes predominant, the time necessary for precharge can be shortened by clamping the main bit line to the precharge voltage in advance. While both the main bit and sub bit lines have heretofore been discharged and set as the ground potential after reading, only each sub bit line is intended for discharge. Clamping the main bit line to the precharge voltage simultaneously with its discharge makes it possible to shorten the time necessary for charge and discharge.
Since the above means does not depend on the configuration of the sense amplifier, it is adaptable even if sense amplifiers of any circuit configuration are used. It is not necessary to change the sense amplifier. The non-volatile memory cell may be a memory which stores multi-valued information as well as binary information.
As one aspect of the present invention, clamp voltage supply elements are disposed every main bit lines as an alternative to the conventional provision of the precharge elements every sense amplifiers. As an alternative to the provision of the discharge elements every sense amplifiers, they are also disposed every sub bit lines. In order to reduce the number of the clamp voltage supply elements, the voltage supply elements may be provided for a common data line (CD) commonly connected to the column switch elements. In this case, all the column switch elements sharing the sense amplifier are brought to an on state in a non-selected state of each memory cell to thereby enable clamp operations for the main bit lines. When the corresponding memory cell is selected, only the column switch to be selected is held in an on state and others are respectively set to an off state.
As one aspect of the present invention, the sub bit line selection switches can be switch-controlled separately every main bit lines sharing the common data line commonly connected to the column switch elements. Only the sub bit line selection switch connected to the main bit line selected by the corresponding column switch element is brought to an on state upon a read operation. The sub bit lines connected to the remaining sub bit line selection switches held off are respectively electrically isolated from their corresponding main bit lines, so that an electrical charge on each main bit line is not wastefully transferred to its corresponding sub bit line unsubjected to the read operation. As another aspect thereof, source line connection selection switch elements which selectively connect source lines of a plurality of non-volatile memory cells to a common source line every main bit lines sharing the common data line commonly connected to the column switch elements, are disposed. The source line connection selection switch element connected to the non-volatile memory cell for each main bit line selected by the corresponding column switch element is brought to an on state upon the read operation. It is thus possible to suppress the useless flowing of a charge current on each bit line in the common source line.
As one aspect of the present invention, the sense amplifier is configured as a current sense type circuit which supplies a current smaller than a current flowing in the corresponding non-volatile memory cell held on when selected by each of the word lines, to each bit line and detects a change in bit line level with respect to a criterion level.
A data processor according to the present invention has an electrically programmable non-volatile memory, and a CPU accessible to the non-volatile memory. The non-volatile memory includes a plurality of non-volatile memory cells, word lines respectively connected to select terminals of the non-volatile memory cells, sub bit lines respectively connected to data terminals of the non-volatile memory cells, main bit lines, sub bit line selection switch elements which selectively connect the sub bit lines to the main bit lines, a sense amplifier connected to the main bit lines via column switch elements, voltage supply elements each of which supplies a predetermined clamp voltage to each main bit line, and discharge elements which discharge the sub bit lines. Each of the voltage supply elements supplies the clamp voltage to the corresponding main bit line before the start and completion of a read operation effected on each non-volatile memory cell. The discharge elements discharge the sub bit lines after the completion of the read operation.
In a manner similar to the above, after the read operation, only the sub bit line is intended for discharge and each of the main bit lines is clamped to the precharge voltage simultaneously with its discharge. It is therefore possible to shorten the time required to perform the charge and discharge. Since the drain (sub bit line) of each memory cell is held at the ground potential when the main bit line is clamped to the precharge voltage, a memory disturb problem does not arise and the speeding up of the read operation can be realized.